The present invention relates to a multi-threshold (MT) CMOS semiconductor circuit system that contains therein semiconductor integrated circuits with MOS transistors having different threshold voltages, to a method for testing semiconductor integrated circuits, and to a method for generating test sequences for testing of semiconductor integrated circuits.
As the dimensions of semiconductor devices are reduced and the level of integration of semiconductor devices is improved, there have been strong demands for low-power semiconductor integrated circuits. The reduction of power supply voltage is an effective way of implementing semiconductor integrated circuits with low power dissipation. The problem is that a reduction in power supply voltage results in slow transistors. A solution to this problem has been proposed. An MT-CMOS semiconductor integrated circuit, as one of semiconductor integrated circuits formed by CMOS semiconductor devices, has been known in the art. In the MT-CMOS semiconductor integrated circuit, two types of MOS transistors are employed, namely low-threshold voltage MOS transistors (low-threshold MOS transistors) and high-threshold voltage MOS transistors (high-threshold MOS transistors).
An MT-CMOS semiconductor integrated circuit is reported in TECHNICAL REPORT OF IEICE, ICD93-107 (1993-10) of THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, which is described with reference to FIG. 13.
FIG. 13 is a circuit diagram which outlines a part of the MT-CMOS semiconductor integrated circuit. FIG. 13 shows that logic gate 99, in which low-threshold transistors (LVth-Tr's) are placed, is connected between power supply terminal 100 at which the operation voltage (VDD) is provided and grounding terminal 101 at which the grounding potential (VGN) is provided. Connected between power supply terminal 100 and logic gate 99 is a p-channel, high-threshold transistor (pHVth-Tr 91). Further, connected between logic gate 99 and grounding terminal 101 is an n-channel, high-threshold transistor (nHVth-Tr 92). Transistors 93-96, contained in logic gate 99, are low-threshold transistors, therefore having the ability to operate at high speed and perform arithmetic operations at high speed, but on the other hand, a large leakage current will flow therein. This may lead to an increase in power consumption. To cope with this problem, HVth-Tr 91 is placed between logic gate 99 and terminal 100 and HVth-Tr 92 is placed between logic gate 99 and terminal 101.
The operation of the MT-CMOS semiconductor integrated circuit of FIG. 13 is described. The electric potential of node 97 between logic gate 99 and pHVth-Tr 91 is the virtual power supply potential (VDDV), while the electric potential of node 98 between logic gate 99 and nHVth-Tr 92 is the virtual grounding potential (VGNV). Electric charges are applied to node 97 that acts as a virtual power supply terminal and to node 98 that acts as a virtual grounding terminal by having HVth-Tr 91 and HVth-Tr 92 placed in the ON state during the operation period of logic gate 99, whereby logic gate 99 formed of LVth-Tr's 93-96 starts operating at high speed. On the other hand, the supply of voltage from terminal 100 to logic gate 99 is cut off by having HVth-Tr 91 placed in the OFF state during the standby period, and HVth-Tr 92 turns off thereby suppressing the leakage current from logic gate 99 to terminal 101 during the standby period. As a result, leakage from terminal 100 to terminal 101 can be held considerably low.
The above-described MT-CMOS semiconductor integrated circuit, however, suffers some problems. For example, when a transistor failure occurs in the MT-CMOS semiconductor integrated circuit, the following inconvenience may occur. Suppose that both HVth-Tr 91 and HVth-Tr 92 fail, for some trouble, to go into the OFF state. Even in such a case, logic gate 99 operates normally, for both HVth-Tr 91 and HVth-Tr 92 are in the ON state when there is an operation command for logic gate 99. On the other hand, when there is a standby command for logic gate 99, both HVth-Tr 91 and HVth-Tr 92 continue to stay in the ON state. In other words, even when trouble causes both HVth-Tr 91 and HVth-Tr 92 to fail to turn off, all the elements of logic gate 99 operate normally thereby producing no ill-effects on the operation of logic gate 99. However, if HVth-Tr 91 and HVth-Tr 92 fail to turn off during the standby period, this results in an increase in the leakage current that flows, via logic gate 99, from power supply terminal 100 to grounding terminal 101. Such an increase makes no sense to the provision of the HVth-Tr's. Accordingly, it becomes impossible to enjoy the foregoing advantages of the MT-CMOS semiconductor integrated circuit, that is, high-speed operations and low power dissipation.
For the case of commonly-used MT-CMOS semiconductor integrated circuits, it is impossible to detect a failure causing HVth-Tr's 91 and 92 to fail to turn off in response to a standby command, as a result of which an increase in the leak-off current cannot be prevented effectively.
The foregoing problems are caused not only by the malfunction of high-threshold transistors but also by the occurrence of short-circuit between a member (e.g., a connection line between the power supply terminal and the logic gate, and an element), or between a member (e.g., a connection line between the logic gate and the grounding terminal, and an element).